Texas Instruments /TM4C123GH6PGE /SYSCTL /DCGCGPIO

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Interpret as DCGCGPIO

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SYSCTL_DCGCGPIO_D0)SYSCTL_DCGCGPIO_D0 0 (SYSCTL_DCGCGPIO_D1)SYSCTL_DCGCGPIO_D1 0 (SYSCTL_DCGCGPIO_D2)SYSCTL_DCGCGPIO_D2 0 (SYSCTL_DCGCGPIO_D3)SYSCTL_DCGCGPIO_D3 0 (SYSCTL_DCGCGPIO_D4)SYSCTL_DCGCGPIO_D4 0 (SYSCTL_DCGCGPIO_D5)SYSCTL_DCGCGPIO_D5 0 (SYSCTL_DCGCGPIO_D6)SYSCTL_DCGCGPIO_D6 0 (SYSCTL_DCGCGPIO_D7)SYSCTL_DCGCGPIO_D7 0 (SYSCTL_DCGCGPIO_D8)SYSCTL_DCGCGPIO_D8 0 (SYSCTL_DCGCGPIO_D9)SYSCTL_DCGCGPIO_D9 0 (SYSCTL_DCGCGPIO_D10)SYSCTL_DCGCGPIO_D10 0 (SYSCTL_DCGCGPIO_D11)SYSCTL_DCGCGPIO_D11 0 (SYSCTL_DCGCGPIO_D12)SYSCTL_DCGCGPIO_D12 0 (SYSCTL_DCGCGPIO_D13)SYSCTL_DCGCGPIO_D13

Description

General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control

Fields

SYSCTL_DCGCGPIO_D0

GPIO Port A Deep-Sleep Mode Clock Gating Control

SYSCTL_DCGCGPIO_D1

GPIO Port B Deep-Sleep Mode Clock Gating Control

SYSCTL_DCGCGPIO_D2

GPIO Port C Deep-Sleep Mode Clock Gating Control

SYSCTL_DCGCGPIO_D3

GPIO Port D Deep-Sleep Mode Clock Gating Control

SYSCTL_DCGCGPIO_D4

GPIO Port E Deep-Sleep Mode Clock Gating Control

SYSCTL_DCGCGPIO_D5

GPIO Port F Deep-Sleep Mode Clock Gating Control

SYSCTL_DCGCGPIO_D6

GPIO Port G Deep-Sleep Mode Clock Gating Control

SYSCTL_DCGCGPIO_D7

GPIO Port H Deep-Sleep Mode Clock Gating Control

SYSCTL_DCGCGPIO_D8

GPIO Port J Deep-Sleep Mode Clock Gating Control

SYSCTL_DCGCGPIO_D9

GPIO Port K Deep-Sleep Mode Clock Gating Control

SYSCTL_DCGCGPIO_D10

GPIO Port L Deep-Sleep Mode Clock Gating Control

SYSCTL_DCGCGPIO_D11

GPIO Port M Deep-Sleep Mode Clock Gating Control

SYSCTL_DCGCGPIO_D12

GPIO Port N Deep-Sleep Mode Clock Gating Control

SYSCTL_DCGCGPIO_D13

GPIO Port P Deep-Sleep Mode Clock Gating Control

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